The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device which may increase an overlay margin in the manufacturing process for obtaining a pad layout to facilitate forming an interconnection region when a negative tone SPT method is applied.
Due to semiconductor devices becoming highly integrated, the size and pitch of patterns for forming circuits needs to be reduced. According to Rayleigh's equation, the size of a fine pattern in a semiconductor device is proportional to the wavelength of light used in the exposure process and is in inversely proportional to the size of a lens in the exposer used for the exposure process. Thus, methods for reducing the wavelength of light used in the exposure process or enlarging the size of the lens used in the exposure process have been used to form fine patterns.
Various photo processes have overcome technical limits in the manufacture of semiconductor devices. For example, masks have been finely designed to adjust the amount of light transmitted through the mask; new photoresist materials have been developed; scanners using a high numerical aperture lens have been developed; and transformed masks have been developed.
However, it is difficult to form a desired width and pitch of a pattern due to limitations of exposure and resolution capacities using currently available light sources, e.g., KrF and ArF. For instance, exposure technologies for manufacturing patterns of about 60 nm have been developed, but making patterns less than 60 nm has been problematic.
Various studies have been conducted to form photoresist patterns having a fine size and pitch.
One of those studies describes a double patterning technology (DPT) of performing double photo processes to form a pattern.
In one example of a DPT, a double exposure etch technology (DE2T) includes exposing and etching a first pattern having a double cycle, and exposing and etching a second pattern having a double cycle between the first patterns. In another example of a DPT, a spacer patterning technology (SPT) includes forming a pattern using a spacer. Both the DE2T and the SPT may be performed using a negative tone and a positive tone.
In the negative tone DE2T, a pattern obtained from a first mask process is removed in a second mask process to form a desired pattern. In the positive tone DE2T, patterns obtained from a first mask process and a second mask process are combined to form a desired pattern. However, the DE2T using two different masks requires additional processes and increases the complexity. Also, it is possible to generate mis-alignment, which is called “overlay,” in the pattern obtained from the first mask process and the second mask process that are separate from each other.
On the other hand, the SPT is a self-aligned method that comprises performing a mask process once to pattern a cell region, thereby preventing mis-alignment.
However, in order to form pad patterns in core and peripheral circuit regions, particularly in outer block of cell mats, an additional mask process is required to isolate each pad patterns. Generally, while plural line-type fine patterns arranged in central block of the cell mat are formed by the SPT, the outer block of the cell mat are not patterned. After forming the plural line-type patterns in the central block, the pad patterns, each connected to each line-type fine pattern, are formed by patterning the outer block of the cell mat. While the outer block is patterned, a mask process for determining a shape of the pad patterns is performed. Then, the additional mask process for removing odds and ends in the outer block is also performed. Also, it is difficult to control deposition uniformity of a spacer forming region and regulate a critical dimension (CD) in a spacer etching process.
Although the SPT is singly applied to a NAND flash process in the case of a multi-layered structure including a line/space, it is difficult to form a pattern by using the SPT if brick wall patterns are provided in a DRAM or complicated pattern layers. In this case, the DE2T is generally used.